? semiconductor components industries, llc, 2010 july, 2010 ? rev. 0 1 publication order number: ndd04n50z/d ndp04n50z, ndd04n50z n-channel power mosfet 500 v, 2.7 features ? low on resistance ? low gate charge ? 100% avalanche tested ? these devices are pb ? free and are rohs compliant absolute maximum ratings (t c = 25 c unless otherwise noted) rating symbol ndp ndd unit drain ? to ? source voltage v dss 500 v continuous drain current r jc i d 3.4 3.0 a continuous drain current r jc , t a = 100 c i d 2.1 1.9 a pulsed drain current, v gs @ 10 v i dm 14 12 a power dissipation r jc p d 75 61 w gate ? to ? source voltage v gs 30 v single pulse avalanche energy, i d = 3.4 a e as 120 mj esd (hbm) (jesd22 ? a114) v esd 2800 v peak diode recovery dv/dt 4.5 (note 1) v/ns continuous source current (body diode) i s 3.4 a maximum temperature for soldering leads t l 260 c operating junction and storage temperature range t j , t stg ? 55 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. i d 3.4 a, di/dt 200 a/ s, v dd bv dss , t j 150 c. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. marking and ordering information v dss r ds(on) (max) @ 1.5 a 500 v 2.7 to ? 220ab case 221a style 5 dpak case 369aa style 2 1 2 3 4 ipak case 369d style 2 1 2 3 4 1 2 3 n ? channel g (1) d (2) s (3)
ndp04n50z, ndd04n50z http://onsemi.com 2 thermal resistance parameter symbol value unit junction ? to ? case (drain) ndp04n50z ndd04n50z r jc 1.6 2.0 c/w junction ? to ? ambient steady state (note 2) ndp04n50z (note 3) ndd04n50z (note 2) ndd04n50z ? 1 r ja 51 40 80 2. insertion mounted 3. surface mounted on fr4 board using 1 sq. pad size, (cu area = 1.127 in sq [2 oz] including traces). electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test conditions min typ max unit off characteristics drain ? to ? source breakdown voltage bv dss v gs = 0 v, i d = 1 ma 500 v breakdown voltage temperature coefficient bv dss / t j reference to 25 c, i d = 1 ma 0.6 v/ c drain ? to ? source leakage current i dss v ds = 500 v, v gs = 0 v 25 c 1 a 150 c 50 gate ? to ? source forward leakage i gss v gs = 20 v 10 a on characteristics (note 4) static drain ? to ? source on ? resistance r ds(on) v gs = 10 v, i d = 1.5 a 2.3 2.7 gate threshold voltage v gs(th) v ds = v gs , i d = 50 a 3.0 4.5 v forward transconductance g fs v ds = 15 v, i d = 1.5 a 2.1 s dynamic characteristics input capacitance c iss v ds = 25 v, v gs = 0 v, f = 1.0 mhz 308 pf output capacitance c oss 43 reverse transfer capacitance c rss 9 total gate charge q g v dd = 250 v, i d = 3.4 a, v gs = 10 v 12 nc gate ? to ? source charge q gs 2.6 gate ? to ? drain (?miller?) charge q gd 6.1 plateau voltage v gp 6.6 v gate resistance r g 5.4 resistive switching characteristics turn ? on delay time t d(on) v dd = 250 v, i d = 3.4 a, v gs = 10 v, r g = 5 9 ns rise time t r 9 turn ? off delay time t d(off) 16 fall time t f 10 source ? drain diode characteristics (t c = 25 c unless otherwise noted) diode forward voltage v sd i s = 3.4 a, v gs = 0 v 1.6 v reverse recovery time t rr v gs = 0 v, v dd = 30 v i s = 3.4 a, di/dt = 100 a/ s 240 ns reverse recovery charge q rr 0.9 c 4. pulse width 380 s, duty cycle 2%.
ndp04n50z, ndd04n50z http://onsemi.com 3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 5.0 10.0 15.0 20.0 25.0 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 1. on ? region characteristics 7.0 v v gs = 10 v 6.5 v 6.0 v 5.5 v 5.0 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 34567891 0 v gs , gate ? to ? source voltage (v) i d , drain current (a) figure 2. transfer characteristics v ds = 25 v t j = 150 c t j = ? 55 c t j = 25 c 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) figure 3. on ? region versus gate ? to ? source voltage i d = 1.5 a t j = 25 c 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4. 0 v gs = 10 v t j = 25 c i d , drain current (a) figure 4. on ? resistance versus drain current and gate voltage r ds(on) , drain ? to ? source resistance ( ) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 ? 50 ? 25 0 25 50 75 100 125 150 r ds(on) , drain ? to ? source resistance (normalized) i d = 1.5 a v gs = 10 v t j , junction temperature ( c) figure 5. on ? resistance variation with temperature 0.90 0.95 1.00 1.05 1.10 1.15 ? 50 ? 25 0 25 50 75 100 125 15 0 t j , junction temperature ( c) bv dss , normalized breakdown voltage (v) i d = 1 ma figure 6. bv dss variation with temperature
ndp04n50z, ndd04n50z http://onsemi.com 4 0.1 1.0 10.0 0 50 100 150 200 250 300 350 400 450 500 v ds , drain ? to ? source voltage (v) i dss , leakage ( a) figure 7. drain ? to ? source leakage current versus voltage t j = 150 c t j = 125 c v ds , drain ? to ? source voltage (v) c, capacitance (pf) figure 8. capacitance variation t j = 25 c v gs = 0 v f = 1 mhz c iss c oss c rss 0 50 100 150 200 250 300 0 2 4 6 8 10 12 0123456789101112 q g , total gate charge (nc) figure 9. gate ? to ? source voltage and drain ? to ? source voltage versus total charge v gs , gate ? to ? source voltage (v) v ds , drain ? to ? source voltage (v) q t q gs v ds = 250 v i d = 3.4 a t j = 25 c v ds v gs q gd 1 10 100 1000 1 10 100 r g , gate resistance ( ) t, time (ns) figure 10. resistive switching time variation versus gate resistance v dd = 250 v i d = 3.4 a v gs = 10 v t d(off) t f t r t d(on) 0.1 1.0 10.0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 125 c t j = 150 c 25 c ? 55 c v sd , source ? to ? drain voltage (v) figure 11. diode forward voltage versus current i s , source current (a) 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 0.01 0.1 1 10 100
ndp04n50z, ndd04n50z http://onsemi.com 5 0.01 0.1 1 10 100 0.1 1 10 100 1000 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 12. maximum rated forward biased safe operating area ndd04n50z v gs 30 v single pulse t c = 25 c 10 s 100 s 10 ms dc 1 ms r ds(on) limit thermal limit package limit 0.01 0.1 1 10 1e ? 06 1e ? 05 1e ? 04 1e ? 03 1e ? 02 1e ? 01 1e+00 1e+01 1e+02 1e+03 pulse time (s) r(t) (c/w) figure 13. thermal impedance (junction ? to ? case) for ndd04n50z 50% (duty cycle) 20% 10% 5.0% 2.0% 1.0% single pulse r ja = 2 c/w steady state pulse time (s) 50% (duty cycle) 20% 10% 5.0% 2.0% 1.0% single pulse r(t) (c/w) figure 14. thermal impedance (junction ? to ? ambient) for ndd04n50z r ja = 40 c/w steady state 1e ? 06 1e ? 05 1e ? 04 1e ? 03 1e ? 02 1e ? 01 1e+00 1e+01 1e+02 1e+03 0.01 0.1 1 10 100
ndp04n50z, ndd04n50z http://onsemi.com 6 ordering information order number package shipping ? ndp04n50zg to ? 220ab (pb ? free) 50 units / rail (in development) ndd04n50z ? 1g ipak (pb ? free) 75 units / rail ndd04n50zt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. marking diagrams a = location code y = year ww = work week g = pb ? free package ndp04n50zg ayww gate source drain 1 gate 2 drain 3 source 4 drain yww 4n 50zg 4 drain 2 drain 1 gate 3 source yww 4n 50zg
ndp04n50z, ndd04n50z http://onsemi.com 7 package dimensions to ? 220 case 221a ? 09 issue af notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. style 5: pin 1. gate 2. drain 3. source 4. drain dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.161 3.61 4.09 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.014 0.025 0.36 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane ? t ? c s t u r j
ndp04n50z, ndd04n50z http://onsemi.com 8 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within dimensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ndp04n50z, ndd04n50z http://onsemi.com 9 package dimensions style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d ? 01 issue b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ndd04n50z/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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